In applications of high voltage step-down (buck) converters, there is a large voltage ripple at the switch node (the common node of the high side and low side switching transistors). Thus, the control circuit of the buck converter is exposed to the high switch voltage and the high bootstrap voltage (BST), which makes the control circuit chip hard to design. In order to overcome this problem, the switch node of the Buck converter may be designed as the reference ground of the control circuit to form a high side buck converter.
However, the high side Buck converter still has a drawback. That is, the reference ground of its output and the reference ground of the control circuit are different. During communication between the output feedback and the control circuit, the output signal can't be directly sensed.
Some control methods are proposed to solve this problem.
FIG. 1 illustrates a prior COT (constant on-time) system 100 wherein a sensing capacitor is used to solve the problem mentioned above.
As shown in FIG. 1, the COT system 100 comprises a first comparator 110. The inverting input terminal of the first comparator 110 is configured to receive a feedback signal VFB, the non-inverting input terminal is configured to receive a reference signal VREF, and the output terminal is coupled to the set terminal S of a RS flip flop 120. The reset terminal R of the RS flip flop 120 is coupled to the output terminal of a second comparator 130, and the output terminal Q of the RS flip flop 120 is coupled to the control terminal of a high side switching transistor M1. The RS flip flop 120 and the second comparator 130 constitute a constant on-time signal generator. The high side switching transistor M1, hereinafter abbreviated as high side transistor M1, may be a device such as triode, MOS, etc. Here, assuming the high side transistor M1 is a NPN transistor, the output terminal Q of the RS flip flop 120 is coupled to the base of the high side transistor M1, an input VIN of the system 100 is coupled to the collector of the high side transistor M1. The non-inverting input terminal of the second comparator 130 is coupled to the emitter of the high side transistor M1, the inverting input terminal is configured to receive a peak current reference signal Ipeak REF. The emitter of the high side transistor M1 is further coupled to one terminal of an output resistor R3, the other terminal of the output resistor R3 is coupled to the cathode of a diode D1 which is used as a low side switching transistor. The anode of the diode D1 is grounded. Hereinafter, the low side switching transistor D1 is abbreviated as low side transistor D1. An output inductor L and an output capacitor Co are serially coupled between the cathode of the diode D1 and the ground. An output VOUT of the system 100 is provided between the output inductor L and the output capacitor Co.
Furthermore, in the system 100, a sensor consisting of a sensing diode D2 and a sensing capacitor C2 is coupled between the system output VOUT and the switch node. The anode of the sensing diode D2 is coupled to the system output VOUT.
In addition, a feedback loop consisting of resistors R1 and R2 is coupled between the cathode of the sensing diode and the switch node, so as to generate a feedback signal VFB (voltage between the resistors R1 and R2) of a sensing signal VSENSE (voltage across the sensing capacitor C2). The feedback signal VFB is provided to the inverting input terminal of the first comparator 110.
During the operation of the system 100, when the feedback signal VFB is lower than the reference signal VREF, the output of the first comparator 110 is logical high. The RS flip flop 120 is set, and its output Q is logical high. The high switching transistor M1 is turned on and the low side transistor D1 is turned off. The system 100 conducts charge operation through the high side transistor M1, the resistor R3, the output inductor L and the output capacitor Co.
Moreover, the current flowing through the high side transistor M1 is gradually increased along with the charge. When the current is larger than the peak current reference signal Ipeak REF, a high level is output by the second comparator 130. The RS flip flop 120 is reset, and its output Q becomes logical low. The high side transistor M1 of the system 100 is turned off. The charge operation is continued through the output inductor L, the sensing diode D2, the sensing capacitor C2, and the resistors R1, R2. The inductor current is gradually decreased. The low side transistor D1 remains OFF until the inductor current chargers the sensing signal VSENSE across the sensing capacitor C2 to the output voltage VOUT. Then the sensing signal VSENSE follows the output voltage VOUT.
The output voltage VOUT, the sensing signal VSENSE and the feedback signal VFB will all decrease when the inductor current falls below the output current. When VFB is decreased to be lower than the reference signal VREF, the output of the first comparator 110 is logical high. The RS flip flop 120 is set, and its output Q is logical high. A new cycle of the system 100 is started.
The system 100 can be analyzed through simply considering the sensing capacitor C2 as a voltage-offtime amplifier whose gain is proportional to its time constant.
For the system 100 shown in FIG. 1, there will be a considerable error if the gain of the voltage-offtime amplifier is not large enough.
Unfortunately, in the system 100, the gain of the sensing capacitor C2 can't be large since the larger the gain (e.g. the larger the time constant), the smaller the signal magnitude. A small signal magnitude may induce the system to be easily affected by noise. Another consideration comes from the system itself, because the sensing signal VSENSE across the sensing capacitor C2 is not always equal to the output voltage VOUT of the system. If the time constant is too large and larger than the time constant of the output capacitor Co, the system will not work accurately since the sensing capacitor C2 can't refresh and sense the output voltage VOUT cycle by cycle.
So, the above analysis shows that the time constant of the sensing capacitor C2 can't be too large, which results in a poor load regulation of the system shown in FIG. 1. The output voltage of the system will be lower under heavy load condition, and higher under light load condition.